Blocking and non-blocking assignments in verilog

the reference answer GPT ᴼ ᴾ ᴱ ᴺ ᴬ ᴵ < br / > in Verilog, each block the statement(the begin - end block) is usually executed in sequence, The execution time therefore depends on the sum of the time required for all the statements contained in the statement block.

In your example, assume that A, B, and y1 through y4 are all single-bit signals, and a non-blocking assignment of one clock cycle is used(< =) and block assignment(=) statements, then the execution time of each statement can be considered one clock cycle. Therefore, each statement takes one clock cycle to execute.

Because the begin-end block contains four statements, the execution time is four clock cycles. If you assume a time unit of 3 per clock cycle, then the time units required to execute this begin-end block should be 12(that is, 4 clock cycles x 3 time units per clock cycle).

In summary, the begin-end block should take 12 units of time to execute, not 9.