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The circuit is implemented using logic gates(AND, OR, NOT) and multiplexers(MUX). Here is a possible implementation:
First, input the last two digits of a as the selection signal into a 2-select 1 multiway selector, and the rest input is 0. When the remainder of a divided by 4 is 0 and the selected signal is 00, MUX's output is the lower four digits of b; When the remainder is 1, the selected signal is 01, and MUX's output is the low four digits of b plus 0x10, that is, the high four positions 1; When the remainder is 2, the selected signal is 10, and the output of MUX is inverted for the high four digits of b, while the low four digits remain unchanged. When the remainder is 3, the selected signal is 11 and MUX's output is switched between the high and low four digits of b. The output of MUX and the input of b are then fed as two inputs into another 2 choose 1 multiplexer, and the result of whether the signal a is divisible by 4(0 or 1) is selected. When divisible by 4, the selected signal is 0, and MUX's output is that the low and high four digits of b are 0; When not divisible by 4, the selected signal is 1, and the output of MUX is the value of the original b.
Here is the logical diagram of the circuit:
where /4 is divided by 4, OR is an OR gate, NOT is a non-gate, and 2 select 1MUX is a 2 select 1 multiway selector.
