HDLbits Question the Lemmings Problem 2

Really don't know what went wrong with my program

//temp存储落地后像左走还是右
module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    reg[1:0] state,next_state,temp;
    parameter left=0,right=1,jump=2;

    always @(posedge clk or posedge areset) begin
        if(areset) state<=left;
        else state<=next_state;
    end

    always @(*) begin
        case (state)
        left:begin
            if(~ground) begin
                next_state<=jump;temp<=left;
            end
            else if(bump_left) next_state<=right;
            else next_state<=left;
        end
        right:begin
            if(~ground) begin
                next_state<=jump;temp<=right;
            end
            else if(bump_right) next_state<=left;
            else next_state<=right;
        end 
        jump:begin
            if(~ground) next_state<=jump;
            else next_state<=temp;
        end
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if(areset) begin
            walk_left= 1;walk_right=0;aaah<=0;
        end
        else begin
            walk_left<= next_state==left;
            walk_right<= next_state==right;
            aaah<= next_state==jump;
        end
    end
endmodule