On the construction of 16 - bit parallel carry arithmetic

Do you think "parallel carry part" is just a title? It's a module?
A C0 comes in, the parallel carry part breaks it down into C4,C8,C12,C16, Then as input to the following 4 ALUs

• The 16-bit parallel carry arithmetic is parallel because it is able to handle the addition operation of 16 input values at the same time, rather than one by one as the serial carry arithmetic does. This means that all input data addition operations can be performed simultaneously, so it is called "parallel".

• In a parallel carry arithmetic, each ALU produces a carry generation signal(often called G) and a carry transfer signal(often called P) indicating whether it needs to be carried to a higher bit and whether it needs to be passed to a higher bit.

• The carry output of C4 through C16 is not the output of each ALU, but is generated by the parallel carry part. The parallel carry unit is a logic circuit that generates the carry output of C4 through C16 based on the carry generation signal and carry transfer signal of all ALUs. The purpose of this widget is to determine which bits need to be carried and how large they should be.

• Thus, while the carry generation and carry transfer signals are generated sequentially for each ALU, the parallel carry unit uses these signals to generate the carry output for C4 through C16 and make all the carry signals effective at the same time.